The present invention relates to a semiconductor memory tester which has an arrangement in which a test pattern is applied to each of a plurality of memory devices under test mounted on a test head, the output from each memory device is subjected to a logical comparison with an expected value for each pin and the result of logical comparison is stored in a fail memory.
FIG. 1 shows a portion of a semiconductor memory tester of this kind. Memory devices under test A1 and A2 are mounted on a first test head 11A and memory devices B1 and B2 are mounted on a second test head 11B. A test pattern, i.e. data and an address, from a pattern generator 15 is applied to the memory devices A1, A2, B1 and B2, in which the data is written at the address and from which the thus written data is read out into logical comparators 16.sub.1, 16.sub.2, 17.sub.1 and 17.sub.2 for comparison with expected values for each pin. The compared results are output from the comparators 16.sub.1, 16.sub.2, 17.sub.1 and 17.sub.2.
Conventionally, these results of comparison are stored in fail memories in the following manner: as depicted in FIG. 2 in which the results of logical comparison for only first pins of the memory devices A1, A2, B1 and B2 are shown, compared outputs A1.sub.1 and A2.sub.1 for the first pins of the memory devices A1 and A2 on the first test head 11A are both applied to multiplexers 18.sub.1 and 182. The multiplexer 181 responds to a select signal S.sub.1 to select and output one of the two inputs thereto, and the multiplexer 18.sub.2 similarly responds to a select signal S.sub.2 to select and output one of the two inputs thereto. Likewise, the results of comparison B1.sub.1 and B2.sub.1 for the first pins of the memory devices B1 and B2 on the second test head 11B are both provided to multiplexers 21.sub.1 and 21.sub.2. The multiplexer 21.sub.1 responds to a select signal S.sub.3 to select and output one of the two inputs thereto, and the multiplexer 21.sub.2 responds to a select signal S.sub.4 to select and output one of the two inputs thereto. The outputs of the multiplexers 18.sub.1 and 21.sub.1 are input into a multiplexer 23.sub.1, which responds to a select signal S.sub.5 to select and output one of the inputs. Similarly, the outputs of the multiplexers 18.sub.2 and 21.sub.2 are input into a multiplexer 23.sub.2, which responds to a select signal S.sub.6 to select and output one of the inputs. The outputs of the multiplexers 23.sub.1 and 23.sub.2 are stored in fail memories 25.sub.1 and 25.sub.2, respectively.
As a result of this, for example, when the select signals S.sub.1 and S.sub.5 are both low, the comparison result Al.sub.1 is stored in the fail memory 25.sub.1, and when the select signals S.sub.2 and S.sub.6 are high and low, respectively, the comparison result B2.sub.1 is stored in the fail memory 25.sub.2. Also for handling results of logical comparisons of the memory devices A1, A2, B1 and B2 for other pins, there are provided multiplexers similar to those 18.sub.1, 18.sub.2, 21.sub.1, 21.sub.2, 23.sub.1 and 23.sub.2 though not shown, and the fail memories 25.sub.1 and 25.sub.2 are adapted to store at respective addresses the results of logical comparisons corresponding to respective pins.
In the case where only one of the test heads 11A and 11B, for example, 11A, is used, the results of logical comparisons for the two memory devices A1 and A2 loaded on the test head 11A can concurrently be stored in the fail memories 25.sub.1 and 25.sub.2. However, when the both test heads 11A and 11B are used, the following problems exist:
(a) Since the multiplexers 23.sub.1 and 23.sub.2 each select either one of the comparison results from the test heads 11A and 11B, all the comparison results for the memory devices A1, A2 and B1, B2 carried by the test heads 11A and 11B, respectively, cannot be output concurrently. In other words, the comparison result for only one of the memory devices, for example, A1 loaded on the test head 11A and the comparison result for only one of the memory devices, for example, B1 on the test head 11B are stored in the fail memories 25.sub.1 and 25.sub.2.
(b) If the comparison results for both of the memory devices, for instance, A1 and A2 on the one test head 11A are simultaneously stored in the fail memories 25.sub.1 and 25.sub.2, the comparison results for the both memory devices B1 and B2 on the other test head 11B cannot be stored in the fail memories 25.sub.1 and 25.sub.2.